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CoreFFT Fast Fourier Transform
Table 6 ? I/O Signal Description (continued)
Signal Name Direction Description
y_valid
read_y
pong
Output
Input
Output
Output complex word valid. Active high. The bit accompanies valid output samples on output busses
y_im and y_re . At any system clock interval while y_valid is active, a complex sample is available on
output busses d_im and d_re.
Read FFT output. Active high. If the signal is active, the module puts out the FFT results in a single burst,
one complex word per clock cycle. The host can insert arbitrary breaks into the burst by deactivating the
signal any time during the burst.
Pong bank of the input buffer is being used by the FFT engine as a working memory.
I/O Interface and Timing
Resetting the Module
Upon reset, the module returns to its initial state with
input and output buffer pointers reset to zero. The input
buffer is now ready to accept a new data frame; signal
load is asserted, and signals y_rdy and y_valid are
deasserted. Both nreset and start reset the module.
Loading Input Data
Input data can be loaded once the signal load is
asserted; otherwise, the module ignores any activity on
the data loading pins. When the host detects an active
load signal, it may begin writing data via the b -bit
busses d_im and d_re . Every valid complex sample must
be accompanied by an active d_valid signal ( Figure 5 on
page 10 ). The module samples d_valid at each rising
edge of the system clock. Once an active d_valid signal is
detected, the core assumes a new complex sample has
been written to the input busses. The module then
writes the new sample to the input buffer. By the next
system clock edge, the module is ready to accept another
input sample. The host can control the input sample rate
via d_valid . Once the module has received N complex
samples, the input buffer is now full, and the module
deasserts the signal load .
Reading Output Data
Once the FFT engine completes another FFT
computational cycle, it asserts the y_rdy signal. The FFT
results are now available for the host in the output
v4.0
buffer. The CoreFFT module puts out the post-processed
complex samples on the two b -bit busses, y_im and y_re .
Every valid complex sample is accompanied by a y_valid
bit. In the basic mode where the host does not control
the FFT output data rate (signal read_y remains
permanently active), all N post-processed complex
samples from a single burst are available consecutively at
each rising system clock edge ( Figure 6 on page 10 ).
During this mode, y_valid remains valid for N system
clock cycles.
The host can control the FFT output sample rate via the
read_y signal. The input read_y acts similarly to an
output clock enable signal: when held HIGH, the module
will continue generating FFT results at each clock edge;
when held LOW, the module will pause in generating.
An example of a controlled output rate mode is depicted
in Figure 7 on page 10 . Every new output sample is valid
for two system clock cycles, as read_y is asserted only
every other clock cycle. (Note that there is latency of one
clock cycle between the signal read_y and a valid sample
output).
The CoreFFT module design does not place any
restrictions on the duty cycle of the read_y signal.
However, for the FFT engine to operate at maximum
efficiency (i.e., no idle time), the post-processed results
must be read out of the output buffer before the engine
needs to write the results of the next data frame (this
time is marked as Accept FFT Result in Figure 3 on
page 6 ). Table 4 on page 6 shows the minimal output
reading rate that does not impact the efficient use of the
FFT engine.
9
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